This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-276796, filed Sep. 12, 2001; and No. 2002-208777, filed Jul. 17, 2002, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a nonvolatile semiconductor memory device such as a flash memory from which data can be electrically erased.
2. Description of the Related Art
In a NOR type flash memory, batch erasing in units of blocks is performed with, e.g., 512 k being determined as one block. Before erasing, as shown in FIG. 1, there are both cells with data xe2x80x9c0xe2x80x9d (programmed state) and cells with data xe2x80x9c1xe2x80x9d (erased state). When the erasing operation is carried out in this state, the threshold voltage of the cell with data xe2x80x9c1xe2x80x9d (erase state) is shifted to a lower threshold voltage. As a result, it may possibly be shifted to a voltage lower than the applied voltage to a non-selected word line in the programming operation or the read operation, e.g., a voltage lower than 0 V.
When a cell whose threshold voltage is excessively lowered, namely, an over erased cell, occurs, an excessive leak current flows to a bit line in the subsequent program or read operation. For example, when the leak current flows to the bit line during the program operation, the program time can be thereby increased. Further, when the leak current flows to the bit line in the read operation, data of all cells connected to that bit line is erroneously detected as data xe2x80x9c1xe2x80x9d, or the erroneous detection does not occur but the reading speed of data xe2x80x9c0xe2x80x9d is decreased.
Therefore, as shown in FIG. 2, a so-called xe2x80x9cpre-erasing programxe2x80x9d operation, by which all the cells are programmed to the level of data xe2x80x9c0xe2x80x9d, is usually performed before carrying out the erasing operation.
When the pre-erasing program operation is carried out, over erasing hardly occurs because all the cells have the data xe2x80x9c0xe2x80x9d before erasing.
In the pre-erasing program operation, the cells having the data xe2x80x9c1xe2x80x9d (erased state) are reprogrammed with the data xe2x80x9c0xe2x80x9d (programmed state). Thereafter, processing advances to the erasing operation. However, in the pre-erasing program operation, the current consumption is high since the channel hot-electron injection is used to program memory cell. Therefore, it is hard to program in many cells at a time, and a very long time is required in order to program all the cells in a block. As memory capacity increases, the number of blocks mounted on the same chip also increases. If the pre-erasing program operation takes time in each block, the time for, e.g., product testing in a factory becomes very long. Of course, due to market demands for data reprogramming at higher speeds, for higher capacity products, it is disadvantageous if data erasing takes time.
A semiconductor integrated circuit device according to a first aspect of the present invention comprises: a programming operation by which a nonvolatile memory cell in an erased state is programmed to a programmed state according to an input program data; a pre-programming operation by which each of the nonvolatile memory cells in the erased state in a memory block including a plurality of nonvolatile memory cells is pre-programmed to an intermediate state between the programmed and erased states; and an erasing operation by which all the nonvolatile memory cells in the memory block are simultaneously erased to the erased state.
A semiconductor integrated circuit device according to a second aspect of the present invention comprises: a programming operation by which a threshold voltage lower than a first voltage for a nonvolatile memory cell is increased to a threshold voltage higher than a second voltage according to an input program data; a pre-programming operation by which a threshold voltage for each of the nonvolatile memory cells in the erased state in a memory block including a plurality of nonvolatile memory cells is increased to a threshold voltage between the first and second voltages; and an erasing operation by which the highest threshold voltage among the threshold voltages for all the nonvolatile memory cells in the memory block is decreased to a threshold voltage lower than the first voltage.
A semiconductor integrated circuit device according to a third aspect of the present invention comprises: a programming circuit by which a nonvolatile memory cell in an erased state is programmed to a programmed state according to an input program data; a pre-programming circuit by which each of the nonvolatile memory cells in the erased state in a memory block including a plurality of nonvolatile memory cells is pre-programmed to an intermediate state between the programmed and erased states; and an erasing circuit by which all the nonvolatile memory cells in the memory block are simultaneously erased to the erased state.
A semiconductor integrated circuit device according to a fourth aspect of the present invention comprises: a programming circuit by which a threshold voltage lower than a first voltage for a nonvolatile memory cell is increased to a threshold voltage higher than a second voltage according to an input program data; a pre-programming circuit by which a threshold voltage for each of the nonvolatile memory cells in the erased state in a memory block including a plurality of nonvolatile memory cells is increased to a threshold voltage between the first and second voltages; and an erasing circuit by which the highest threshold voltage among the threshold voltages for all the nonvolatile memory cells in the memory block is decreased to a threshold voltage lower than the first voltage.
A semiconductor integrated circuit device according to a fifth aspect of the present invention comprises: a programming operation by which a nonvolatile memory cell in an erased state is programmed to one of at least two programmed states according to an input program data; a pre-programming operation by which each of the nonvolatile memory cells in the erased state in a memory block including a plurality of nonvolatile memory cells is pre-programmed to an intermediate state between one of the programmed states and erased state; and an erasing operation by which all the nonvolatile memory cells in the memory block are simultaneously erased to the erased state.
A semiconductor integrated circuit device according to a sixth aspect of the present invention comprises: a programming operation by which a threshold voltage lower than a first voltage for a nonvolatile memory cell is increased to a threshold voltage higher than one of at least two different voltages according to an input program data; a pre-programming operation by which a threshold voltage for each of the nonvolatile memory cells in the erased state in a memory block including a plurality of nonvolatile memory cells is increased to a threshold voltage between one of the at least two different voltages and first voltage; and an erasing operation by which the highest threshold voltage among the threshold voltages for all the nonvolatile memory cells in the memory block is decreased to a threshold voltage lower than the first voltage.